FPGA Learning Steps
1. Basic digital design using HDL (Verilog/VHDL) 
 - www.chipverify.com
 - nandland.com
 - www.asic-world.com
 - Test your Verilog Knowledge here

2. Simulate your HDL
 a. Creating Testbench
    - Testbench from Asic-World
    - Testbench from ChipVerify
 b. Online Simulator
  * Interactive Simulator : Tutorial & Example 
  * EDA Playground : Tutorial & Example
 c. Modelsim Simulation 
  - Installation of modelsim (altera 'free')
  - Modelsim Tutorial : EN-ID + design-files
 d. DE-board Simulation : DE-Sim - version
  - Installation of DE-Sim - Installer files 
  - DE-Sim Tutorial : EN-ID

3. Implement simple Design in FPGA Board
 a. Know your board: 
  - DE10-Standard: Intro - Manual:EN-ID
  - DE10-Nano    : Intro - Manual:EN-ID
  - DE10-Lite    : Intro - Manual:EN-ID
  - DE1-SoC      : Intro - Manual:EN-ID
 b. Using FPGA IDE (Quartus Prime Lite v20.1)
  - Installation of Altera-Quartus
  - Quartus Tutorial using Verilog entry : EN-ID
  - Quartus Tutorial using Schematic entry : EN-ID
  - Quartus for DE-Boards
 c. Downloading Your first FPGA design
  - DE10-Standard: MyFirstFPGA, video, Files
  - DE10-Nano    : MyFirstFPGA, video, Files 
  - DE10-Lite    : MyFirstFPGA, video, Files
  - DE1-SoC      : MyFirstFPGA, video, Files
4. Sharpen your FPGA Skill (from FPGAcademy.org)
 a. Digital Logic LabWork
 b. Computer Organization LabWork
 c. Computer Acceleration LabWork
 d. Embedded System LabWork
5. Implementing Processor inside FPGA
 a. Embedded development SW : EDS-ide; eclipse
 b. Soft Processor System : NIOS
  - Nios-II "Hello World"
  - Nios-II Peripheral SPI : video
  - Nios-V (risc-v) "hello world" : video
 c. Hard Processor System (HPS) inside FPGA
  - First HPS Design : 
   -- DE10-Standard 
   -- DE10-Nano 
   -- DE1-SoC
6.Using others IP-Core 
 a. Source of open-core : opencores
 b. verification
 c. RISC-V Processor Cores
 d. Integrating many ip-core

https://github.com/abdelazeem201/Introduction-to-System-on-Chip-Design-Online-Course